This invention relates to an improved frequency divider for dividing the frequency of an output pulse from a crystal oscillating circuit by a counter formed of a plurality of complementary insulated gate field effect transistors (abbreviated as "IGFET's").
FIG. 1 illustrates a prior art frequency divider provided with a binary counter formed of complementary IGFET's. An output from a crystal oscillating circuit 1 is supplied to the junction of the gates of a P channel type IGFET 2 and an N channel type IGFET 3 jointly constituting a first inverter 4. The IGFET's 2, 3 are connected in series between two power supply terminals, namely between a V.sub.DD terminal and the ground to constitute a complementary IGFET type inverter. An output .phi. from the first inverter 4 is conducted from the output terminal of the first inverter 4, that is, the junction of the IGFET's 2, 3 to the input terminal of a second inverter 5, that is, the gate junction of IGFET's 6, 7 constituting the second inverter 5. An output from the second inverter 5 is sent forth from the junction of the IGFET's 6, 7 in the form .phi. inverted from the output .phi. from the inverter 4. The output .phi. from the first inverter 4 is transferred to the gate of an N channel type IGFET 10 included in a first complementary unit circuit 9 of a binary counter 8 and also to the gate of a P channel type IGFET 12 included in a second complementary unit circuit 11. An output .phi. from the second inverter 5 is delivered to the gate of a P channel type IGFET 13 included in the first complementary unit circuit 9 and also to the gate of an N channel type IGFET 14 included in the second complementary unit circuit 11. An output from the binary counter 8 is conducted to an output terminal 18 of said counter 8 through an inverter 17 formed of IGFET's 15, 16, and also fed back to the gate junction of IGFET's 19, 20 included in the first complementary unit circuit 9. An output from said first complementary unit circuit 9 is carried from the junction of the series connected IGFET's 19, 20 to the gate junction of IGFET's 21, 22 of the second complementary unit circuit 11.
With the prior art frequency divider of FIG. 1, an output .phi. from the first inverter 4 has a pulse wave form whose higher level represents V.sub.DD volts and whose lower level denotes a zero volt as shown in FIG. 2(a). Therefore, an output B from the second inverter 5 is a pulse .phi. having an opposite polarity to the output .phi. from the first inverter 4 as shown in FIG. 2(b). Namely, said output .phi. from the second inverter 5 is of the same polarity as an input to the first inverter 4, that is, an output A from the crystal oscillating circuit 1.
Now let it be assumed that an output from the inverter 17 has a logic level of "0" at time t1, as shown in FIG. 2(e). Then, an input having a logic level of "0" is supplied to the input terminal of the first complementary unit circuit 9, causing the IGFET 19 to be rendered conducting and the IGFET 20 to become inoperative. Since, at this time, the pulse .phi. also has a logic level of "0", the IGFET 13 is rendered conducting, and an output C from the first complementary unit circuit 9 has a higher level of "1" as shown in FIG. 2(c). When the level of the pulse .phi. is changed to "0" at time t2, then an output B from the second inverter 5 has its logic level shifted to "1", causing the IGFET 13 to become inoperative. Since, however, the IGFET 10 also becomes inoperative at this time, the logic level of the output C from the first complementary unit circuit 9 does not indicate "0", but is kept at "1". The output C causes the IGFET 21 of the second complementary unit circuit 11 to be rendered inoperative and the IGFET 22 to become operative. The IGFET 14 is also rendered conducting upon receipt of the pulse .phi. having a logic level of "1". Therefore, an output D from the second complementary unit circuit 11 has its logic level changed to "0", as shown in FIG. 2(d). At time t3, the .phi. signal has a logic level of "1", and the .phi. signal has a logic level of "0". Consequently, an output C from the first complementary unit circuit 9 has its logic level shifted to "0", as shown in FIG. 2(c), while an output D from the second complementary unit circuit 11 has its logic level kept to "0". Therefore an output E from the frequency divider has its logic level kept at "1". At time t4, an output C from the first complementary unit circuit 9 has its logic level kept at "0". An output D from the secondary complementary unit circuit 11 has its logic level shifted to "1", and an output E from the frequency divider has its logic level shifted to "0". When the above-mentioned cycle of operation continues to time t6, then the frequency divider issues one output E for every two periods of a clock pulse .phi. represented by times t2 to t6. This means that the clock pulse .phi. or .phi. has its frequency divided into halves.
FIG. 1 shows one stage of a binary counter constituted of a plurality of complementary unit circuits. Where this binary counter is used with an electronic timepiece or other electronic devices, a plurality of said counters are connected in series as shown in FIGS. 3 or 4.
In the case of FIG. 3, an output .phi. from the crystal oscillating circuit 1 is supplied to the .phi. input terminal of a first stage binary counter 23 and an output .phi. from an inverter 24 is conducted to the .phi. input terminal of said first stage binary counter 23. Outputs Q.sub.1, Q.sub.1 from the binary counter 23 are supplied to the .phi., .phi. input terminals of the succeeding binary counter 25 respectively. Similarly, outputs Q.sub.2, Q.sub.2, Q.sub.3, Q.sub.3 from the binary counters 25, 26 are delivered to the .phi., .phi. input terminal of each of succeeding binary counters 26, 27. Since the prior art frequency divider of FIG. 3 comprises four binary counters 23, 25, 26, 27, an output clock pulse from the crystal oscillating circuit 1 has its original frequency divided to an extent of 1/2.sup.4, that is, into sixteenth parts at the output terminal of the last counter 27. The prior art frequency divider of FIG. 3 comprises an inverter 1a, crystal oscillating element 1b, resistor 1c, input capacitor 1d and output capacitor 1e connected between both ends of the resistor 1c and the ground.
With another prior art frequency divider of FIG. 4, an output clock pulse from the crystal oscillating circuit 1 is sent forth to the .phi. input terminal of the binary counter 23 through first and second inverters 28, 29. An output from the inverter 28 is conducted to the .phi. input terminal of said binary counter 23. In other respects, the prior art frequency divider of FIG. 4 is arranged and operated in the same manner as that of FIG. 3. The inverters 28, 29 are used for the shaping of clock pulses.
Generally, with f.phi. taken to denote the frequency of an output clock pulse from a crystal oscillating circuit 1, n to indicate a number of binary counters used, then an output from the last stage binary counter has a frequency f0 expressed as f0 = f.phi./2.sup.n.
For example, where the frequency f.phi. of the crystal oscillating circuit 1 is 4.194304 MHz and binary counters are provided in a number of four stages, then an output from the last binary counter has a divided frequency f0 of 262.144 KHz.
The above-mentioned prior art frequency dividers have the drawbacks that since an output clock pulse from a crystal oscillating element 1b does not take a thoroughly rectangular waveform, it is necessary to provide waveform shapers such as inverters 28, 29 shown in FIG. 4, leading to considerable power consumption in said inverters 28, 29. For example, when the crystal oscillating element 1b has a frequency of 4.194304 MHz and a power source V.sub.DD has 3 volts, then the inverter 1a consumes power of 90 .mu.w and the inverter 28 60 .mu.w, thus appreciably increasing an amount of power consumed by the inverters 28, 29. An electronic timepiece, for example, is generally operated over a year by a single or two dry cells. From this point of view, the inverters are preferred to consume as little power as possible, and particularly, the inverters 28, 29 are demanded to consume no power.
With the 2-phase binary counter, a frequency divider gets unstable or erroneous in operation when phase difference exists between the signals .phi., .phi.. Particularly, the higher the frequency of the crystal oscillating element 1b, the more deformed the waveform of an output from the inverter 1a. This event makes it necessary to provide a shaping inverter, and results in complicated circuit arrangement and large power consumption.